In a ULSI device manufacturing process, a variety of process flows are performed in accordance with the constitution of a device. For example, in a high-temperature heat treatment process or the like, heavy metal impurities, typified by Fe, Ni, Cu, can cause the formation of defects or an energy level near the surface of a wafer resulting in the degradation of device characteristics. These heavy metal impurities must therefore be removed from the vicinity of the wafer surface, and in order to achieve this, IG (Intrinsic Gettering) and various EG (Extrinsic Gettering) gettering techniques are used.
Generally, oxygen precipitate nuclei, which make impurity gettering possible, are scattered about in large numbers in a silicon single crystal grown using the Czochralski method or the magnetic Czochralski method (hereinafter referred to as the CZ method). These oxygen precipitate nuclei are introduced during the process of growing a silicon single crystal, and the higher the oxygen concentration, the more numerous the oxygen precipitate nuclei.
In a conventional high-temperature device process, having a Well Drive process, because oxygen precipitation occurs relatively easily during device process heat treatment, forming sufficient BMD for gettering in bulk, NIG (Natural IG), DZ(Denuded Zone)-IG gettering has come into widespread use.
In the device process of the future, it has become clear that manufacturers will promote low-temperature processes that strive for yet higher levels of integration, and make use of high energy ion implantation. In that case, the in-process formation of BMD is expected to become a problem because of the move to low-temperature processing.
Therefore, in a low-temperature process, it is difficult to achieve an adequate IG effect as with a high-temperature process. Further, it is believed that even with a low-temperature process, it will be hard to avoid heavy metal impurities from high energy ion implantation and other factors, making gettering technology imperative.
Meanwhile, higher integration levels require that quality be increased even further in the near surface region of the wafer. Since, unlike a CZ-Si wafer, there are absolutely no Grown-in defects in an epitaxial layer, an epitaxial wafer has extremely high quality surface integrity. But until now, the use of epitaxial wafers has been limited by cost factors.
However, due to the problem of Grown-in defects, there is an extremely high likelihood that epitaxial wafers will be utilized in earnest in even higher integration next-generation devices (64MB, 256MB DRAM era). And epitaxial wafers are viewed as being the most likely candidates for 12-inch wafers as well.
To date, DZ-IG processing has been widely used to enhance the quality of the ordinary CZ-Si wafer. With this approach, a two-stage high temperature and low temperature heat treatment is performed. First, oxygen near the surface of a wafer is diffused toward the outside, interstitial oxygen, which constitutes the nuclei of microdefects, is reduced, and a DZ(Denuded Zone) layer, in which there are no defects in the device active area, is formed by subjecting a wafer to high-temperature heat treatment at between around 1100.degree. C. and 1200.degree. C. Thereafter, oxygen precipitate nuclei are formed in the wafer bulk via low-temperature heat treatment at between 600.degree. C. and 900.degree. C. However, with DZ-IG processing, grown-in defects exist in the device active area.
If this wafer is subjected to a high-temperature device process, oxygen precipitate nuclei grow into oxygen precipitates in accordance with the high-temperature heat treatment of the process, and a sufficient IG effect is exhibited. But with DZ-IG processing, problems arise in a state-of-the-art device process, such as residual Grown-in defects in the device active area, and the lack of in-process growth of sufficient oxygen precipitates in low-temperature device processing.
If the oxygen precipitation behavior of p/p++, p/p+, p/p- epitaxial wafers is compared, in a p/p++ epitaxial wafer, that has a high concentration of B in the substrate (substrate resistivity &lt;10 m.OMEGA..multidot.cm), oxygen precipitation occurs extremely easily in accordance with the effect of the high concentration of B. As shown in FIG. 3, sufficient BMD for gettering are formed, and an adequate IG effect can be expected even in a low-temperature process, and even in a low oxygen concentration substrate ([Oi]=12.times.10.sup.17 atoms/cm.sup.3 old ASTM, hereinafter omitted) for an epitaxial wafer with a substrate resistivity of less than 6 m.OMEGA..multidot.cm, and in a high oxygen concentration substrate ([Oi]=15.times.10.sup.17 atoms/cm.sup.3) for an epitaxial wafer with a substrate resistivity of between 8.about.10 m.OMEGA..multidot.cm.
Furthermore, FIG. 3 shows the results of selectively etching (5 minute Wright Etch) a wafer, and measuring BMD density using an optical microscope after using 8-inch outside diameter, p(100)B-doped substrates with initial oxygen concentrations of 12.times.10.sup.17 atoms/cm.sup.3 and 15.times.10.sup.17 atoms/cm.sup.3 to prepare a variety of epitaxial wafers with different substrate resistivity, and subjecting these wafers to the pattern of low-temperature process heat simulation shown in FIG. 1.
Further, the results of comparing the oxygen precipitation behavior of an epitaxial wafer and a polished wafer in a high-temperature process flow are shown in FIG. 4. FIG. 4 shows the results of selectively etching (5 minute Wright Etch) a wafer, and using an optical microscope to measure BMD density after utilizing 8-inch outside diameter, p(100)B-doped substrates with two types of substrate resistivity, 10.about.20 m.OMEGA..multidot.cm(p+) and 10.OMEGA..multidot.cm(p-), to prepare mirror polished wafers with initial oxygen concentrations varying in the range of 11.about.17.times.10.sup.17 atoms/cm.sup.3, and epitaxial wafers, the epitaxial layers of which were grown on wafers from the same lot as the mirror polished wafers, and subjecting these wafers to the pattern of high-temperature process heat simulation shown in FIG. 2.
When a mirror polished wafer is subjected to a high-temperature device process, oxygen precipitate nuclei grow to become oxygen precipitates in accordance with the high temperature heat treatments in the process, exhibiting an adequate IG effect.
Conversely, with an epitaxial wafer having resistivity of 10 m.OMEGA..multidot.cm or higher, oxygen precipitate nuclei shrink or disappear as a result of the high-temperature heat histories at epitaxial growth, and oxygen precipitation is apparently suppressed considerably compared to that of a mirror polished wafer. It became clear that little if any BMD is formed, and the IG effect cannot be expected with an epitaxial wafer having substrate resistivity of 10 m.OMEGA..multidot.cm or higher in either a low-temperature process or a high-temperature process, even when a substrate with a fairly high oxygen concentration is utilized.
Methods for performing pre-epitaxial growth heat treatment in order to achieve a sufficient IG effect have already been studied. In H. Tsuya et al.: APPI. Phys. Lett. 36 (1980) 658, heat treatment conditions calling for temperatures of between 620.degree. C. to 1150.degree. C. for between 16 hours and 64 hours in an oxygen atmosphere were studied, and indicated that heat treatment at 820.degree. C. for 16 hours is effective for gettering. However, the evaluation of BMD was performed after heat treatment at 1140.degree. C. for 2 hours on the assumption of a high temperature process, and the effect of the low-temperature process was not clear. There was also the problem that a heat treatment time of 16 hours or more is extremely long.
Further, Japanese Patent Publication No. 4-56800 reports a 2-stage heat treatment method, wherein, prior to epitaxial growth, a hightemperature heat treatment (1000.about.1100.degree. C.) is added following a low-temperature heat treatment (500.about.900.degree. C.). But this is a low temperature + high temperature 2-step heat treatment, a high cost, long duration heat treatment, and slippage and contamination problems associated with high-temperature heat treatment must also be considered.
Japanese Patent Laid-open No. 8-97220 proposes a method, wherein, during the process in which the temperature is increased in the epitaxial growth process, either the rate of increase in a temperature range of from 800.degree. C. to 1000.degree. C. is less than 15.degree. C./min, or an arbitrary temperature is maintained for between 5.about.100 minutes. With this method, there is a clear drop in epitaxial throughput, and this method is also problematic in that the current situation requires the low cost, stable manufacture of epitaxial wafers.
As described above, epitaxial wafers are viewed as prime candidates for use as next-generation device wafers, but in the past it was difficult to achieve a sufficient IG effect in an epitaxial wafer, especially a p-type (B-doped) wafer having a substrate resistivity of 10 m.OMEGA..multidot.cm or higher, using a low-temperature device process, even when a substrate with a high oxygen concentration was used.